Multi-bit quantizers are commonly encountered in flash ADCs, pipeline ADCs etc. High-speed flash ADCs or multi-bit quantizers require fast comparators with a threshold voltage varying over the complete input range of the ADC. The basic architecture is shown in FIG. 1 where all comparators 10, (i=1, . . . , N−1) are identical and compare the sampled input voltage to different threshold voltages Vth,i that span a wide input range, e.g., the complete input range of the flash ADC. For simplification, FIG. 1 depicts the single-ended variant rather than the more commonly used differential structure.
When realizing the comparators of FIG. 1, it is desirable that they be operable with a wide range of threshold voltages Vth to match the input range with the maximum available voltage range. In recent technologies the supply voltage drops, thus leaving less voltage room on top of a large threshold voltage. An obvious approach could be to provide dedicated comparators for different ranges of threshold voltages. However, this would clearly be an expensive solution.
A general representation of the conventional PMOS input stage of a dynamic comparator is shown in FIG. 2. During the reset phase the switches SW1p and SW1n are closed and the nodes Dip and Din are reset to the electrical ground. During the comparison phase the switch SW2 is closed and the voltages on the nodes Dip and Din increase, building up a voltage difference dependent on the input voltage Vin_p−Vin_n. Capacitors CDp and CDp in FIG. 2 represent the parasitic capacitance on the nodes Dip and Din. They can be increased by adding explicit capacitors to achieve low-noise comparators. The latch circuit is triggered when the latch threshold is reached and the difference between the voltages on Dip and Din is large enough to get a decision.
Other solutions can be envisaged. For example, the threshold voltage can be subtracted from the input signal in front of the comparator. The comparator then only has to compare the resulting voltage with a zero threshold. This subtraction is typically done by switching the top plate of the sampling capacitor CS to the threshold voltage Vth before activating the comparator 10 (see FIG. 3). This extra switching operation between the sampling moment and the start of the comparison, required to do the voltage subtraction, limits the speed. The settling time to generate this voltage difference is mainly determined by the switch resistance and the parasitic capacitance at the comparator input. They both should be kept low, which requires large switches and small input transistors of the comparator, which increases the offset and limits the current through the input pair and, hence, the comparator speed. The non-linear parasitic capacitance of the input transistor further results in a non-linear attenuation of the input signal. Finally, there needs to be a capacitive network for each threshold level, which increases the total input capacitance of the ADC.
Another solution to subtract the threshold voltage is to use a second input pair as depicted in FIG. 4. This solution does not impose a speed penalty nor does it increase the total input capacitance or power consumption. Also, this solution ensures both transistors in each of the pairs T1_p, T1_n and T1_p*, T1_n* see more or less the same voltages when the input voltage is substantially similar to that of the threshold. However, this comparator still operates slowly if one of the pairs is cut off, which happens for high threshold voltages. In addition, the common-mode of the input pairs becomes signal-dependent in this configuration. The latter can be solved by putting the reference voltages on one input pair and the input signals on the other. However, this configuration gives the problem that one side of the input pair is cut off while the other one has a large overdrive, making accurate comparison difficult.
The threshold voltage can also be built into the differential structure of the comparator. However, a mismatch can be created by choosing different sizes for the input transistor, different values for the capacitors CDp and CDn, different voltages of the bulk of the input transistors or by adding compensation current sources. This works for calibrating out relatively small offset values, so that if the input voltage is substantially similar to that of the threshold voltage, both transistors of the input pair have a similar overdrive voltage. However, when a large threshold voltage is desired, one side of the input pair is cut off whereas the other one experiences a large overdrive, making it difficult for the comparator to operate. As a result, these techniques only work for a limited range of threshold voltages.
Hence, there is a need for comparators with an input stage wherein the above-mentioned limitations are avoided or overcome.